The structure and formation of non-volatile memory cells of Superflash

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Abstract

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

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About the authors

D. A. Abdullaev

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Author for correspondence.
Email: abdullaev.d@inme-ras.ru
Russian Federation, Moscow

E. V. Bobrova

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: abdullaev.d@inme-ras.ru
Russian Federation, Moscow

R. A. Milovanov

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: abdullaev.d@inme-ras.ru
Russian Federation, Moscow

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Supplementary files

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2. Fig. 1. Diagrams of vertical sections of the SuperFlash 1st (a), 2nd (b) and 3rd (c) generations with tables of operating modes [6-10].

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3. Fig. 2. The main stages of the formation of the 1st generation SuperFlash YAP using the LOCOS process [13].

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4. Fig. 3. The sequence of stages of formation of the 2nd generation SuperFlash YAP using a triple self-displacement process [16, 18].

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5. Fig. 4. The scheme of integration of the main stages of SF memory formation of the 3rd generation (in blue) in 40 nm, the GlobalFoundries process technology (in black) [23].

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6. Fig. 5. SEM images of vertical sections of 1st generation SF memory transistors along BL (a, b) and SL (c, d).

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7. Fig. 6. SEM images of vertical cross sections of 1st generation SF memory transistors along the bitline made according to technological standards of 500 nm (a), 350 nm (b), 300 nm (c) and 250 nm (d).

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8. Fig. 7. SEM images of vertical sections of 2nd generation SF memory transistors along BL (a, b) and SL (c—e).

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9. Fig. 8. SEM images of vertical sections of SF memory transistors of the 3rd generation along BL (a, b) and SL (c, d).

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