Vol 53, No 3 (2024)

The influence of nonuniformity properties of the LiCoO₂ cathode film deposited by magnetron sputtering on the capacity of all-solid-state thin-film lithium-ion batteries (ASSLib) was studied. It was found that the film nonuniformity corresponds to the magnetron plasma density distribution and the angular distribution of sputtered particles. The capacity distribution of the ASSLib with LiCoO₂ cathode depending on the distance to the substrate center was studied. The maximum capacity corresponded to the dense part of the toroidal region of the magnetron plasma. It was determined that the main causes of batteries capacity decline in the central part and on the edge of the substrate are the impurity phase of lithium cobaltate and the smaller thickness of the cathode layer, respectively.

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.

The theoretical model proposed earlier by the authors, which describes the interrelation of strength and electromigration (diffusion) properties of interfaces formed by joined materials, has been perfected and extended. Within the framework of the developed model, a linear relationship between the values of the work of reversible interface separation W_a and the activation energy of electromigration in the interface H_EM was established. The coefficients of the obtained relation are estimated and compared with experimental data on the study of electromigration in a copper conductors covered with protective dielectrics. Using also the model developed earlier by the authors, which describes the dependence of the value on the concentrations of non-equilibrium lattice defects in the volumes of joined materials, a number of effects due to the influence of such defects on the processes caused by electromigration have been predicted and investigated. In the paper we obtained that by introducing non-equilibrium lattice defects in the volumes of bonded materials in the form of atomic impurities of interstition or substitution it is possible to effectively influence the characteristics of electromigration instability of the shape of the interlayer interface. For the introduction impurities, quantitative analytical estimates of the impurity concentration necessary for a significant change (both increase and decrease) in the characteristic rise time of the instability of the shape of the initially flat interface have been obtained.

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

The conditions for the growth of n-type Ge conduction layers by the HW CVD method with the parameters required to create a Ge-TIR transistor with an induced p-type channel are determined. The conditions of deposition by electron beam deposition and subsequent annealing of layers of a high-k dielectric ZrO₂:Y₂O₃ are optimized, allowing to achieve a leakage current of 5 × 10^–6 A/cm². For the developed instrument structure, some parameters of the Ge-TIR transistor were calculated, such as the channel length, the maximum voltage between the drain and the source, and the breakdown voltage.

The electrophysical properties of instrument MOSFET structures (capacitor, field-effect transistor with an isolated gate and an induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. Static and dynamic characteristics were measured. The theoretical study was carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristic of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of the structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, the photovoltaic effect in p—n junctions, the photo-Dember effect and tunneling of charge carriers through a gate dielectric. The results of the work are of interest from the point of view of creating high-speed transistors and integrated circuits of a new type.